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TPS40193DRCRG4  控制器 IC REG CTRLR BUCK PWM VM 10SON
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US $0.80 / PCS
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數量
 PCS
金額
US $0.80
 
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產品詳情
型號TPS40193DRCRG4
封装10-VFDFN Exposed Pad
品牌Texas Instruments
年份17+
描述控制器 IC REG CTRLR BUCK PWM VM 10-SON
 規格書點擊查看

Texas Instruments TPS40193DRCR

TPS40192 and TPS40193 are cost-optimized synchronous buck controllers that operate from 4.5 V to 18 V input. These controllers implement a voltage-mode control architecture with the switching frequency fixed at either 600 kHz (TPS40192) or 300 kHz (TPS40193). The higher switching frequency facilitates the use of smaller inductor and output capacitors, thereby providing a compact power-supply solution. An adaptive anti-cross conduction scheme is used to prevent shoot through current in the power FETs.

Short circuit detection is done by sensing the voltage drop across the low-side MOSFET when it is on and comparing it with a user selected threshold of 100 mV, 200 mV or 280 mV. The threshold is set with a single external resistor connected from COMP to GND. This resistor is sensed at startup and the selected threshold is latched. Pulse-by-pulse limiting (to prevent current runaway) is provided by sensing the voltage across the high-side MOSFET when it is on and terminating the cycle when the voltage drop rises above a fixed threshold of 550 mV. When the controller senses an output short circuit, both MOSFETs are turned off and a timeout period is observed before attempting to restart. This behavior provides limited power dissipation in the event of a sustained fault.

For all available packages, see the orderable addendum at the end of the data sheet.
德克萨斯仪器TPS40193DRCR
tps40192和tps40193成本优化的同步降压控制器,操作从4.5 V至18 V输入。这些控制器实现电压模式控制架构与开关频率固定为600千赫(tps40192)或300千赫(tps40193)。较高的开关频率便于使用较小的电感器和输出电容,从而提供了一种紧凑的电源解决方案。一种自适应反交叉传导机制是用来防止直通电流的功率场效应管。
短路检测是通过检测低侧MOSFET的电压降时进行的,并将其与用户选择的100毫伏、200毫伏或280毫伏的阈值进行比较。阈值是设置一个单一的外部电阻从COMP连接到GND。该电阻器在启动时被检测到,所选的阈值被锁存。脉冲通过脉冲限制(防止电流失控)是通过感应高侧MOSFET的电压时,它是和结束周期时,电压下降超过550 mV的固定阈值上升。当控制器检测到输出短路时,在试图重新启动之前,两个MOSFET都被关闭,超时时间被观察到。这种行为在持续故障时提供有限的功率耗散。
所有可用的软件包,在数据表的末尾看到有序的补遗。
 
 
 

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